1. Technical Field
The present invention relates to a wiring board for mounting a semiconductor element.
2. Background
Conventionally, the wiring board for mounting a semiconductor element has a multi-layer structure where a plurality of insulating layers and conductor layers are alternately laminated (for example, Japanese Unexamined Patent Publication No. 2000-31329). On a central portion of the upper surface of the wiring board, a mounting portion for mounting a semiconductor element is formed. On the upper surface and the lower surface of the multi-layer structure, a part of the conductor layer is exposed, and furthermore, a solder resist layer is deposited thereon. In the mounting portion, a plurality of semiconductor element connection pads to be flip-chip connected to electrodes of the semiconductor element are arranged in a lattice shape. The substantially entire surface of the lower surface of the wiring board is an external connection surface for connecting with the outside. A plurality of external connection pads for connecting with an external electric circuit board are arranged in a lattice shape on the lower surface. The semiconductor element connection pad includes those for signal, for grounding, and for power supply. Likewise, the external connection pad also includes those for signal, for grounding, and for power supply. Each of the semiconductor element connection pads is electrically connected to the corresponding one of the external connection pads through the internal conductor layer.
The semiconductor element connection pads for power supply and for grounding are mainly arranged in the central portion of the mounting portion. The semiconductor element connection pads for signal, for grounding, and for power supply are arranged in a mixed manner in the outer peripheral portion of the mounting portion. The semiconductor element connection pads for signal, for grounding, and for power supply arranged in the outer peripheral portion of the mounting portion form a small group of pad group where the respective sets of a plurality of pads are arranged in a predetermined positional relation. Here, the individual region where this pad group is formed is referred to as a “segment region”.
In FIG. 2, a top view of a general wiring board is shown. A segment region B occupies a part of the outer peripheral portion of a mounting portion A of the wiring board. A plurality of such the segment regions B are present in the outer peripheral portion of the mounting portion A. An example of arrangement of the semiconductor element connection pads for signal S, for grounding G, and for power supply P in the segment region B is shown. It should be noted that “S” represents the semiconductor element connection pad for signal, “G” represents the semiconductor element connection pad for grounding, and “P” represents the semiconductor element connection pad for power supply. In FIG. 2, the semiconductor element connection pads S, G and P in the segment region B include five columns L1 to L5 along the outer periphery side of the mounting portion A. The semiconductor element connection pads for grounding G are arranged on the outermost column L1 and the innermost column L5 in the segment region B. The semiconductor element connection pads for power supply P are arranged on the column L3 in the center. On the column L2 between the L1 and the L3, and on the column L4 between the L3 and the L5, the semiconductor element connection pads for signal S are arranged in the central portion, and the semiconductor element connection pads for grounding G and for power supply P are arranged at both ends thereof.
A part of the conductor layer at an uppermost layer are exposed from the circular openings provided in the solder resist layer, whereby these semiconductor element connection pads S, G, and P are formed. In FIGS. 3A to 3D, a conductor layer 11 at the uppermost layer and conductor layers 12 to 14 formed below the conductor layer 11 in the vicinity of the segment region B of the conventional wiring board are shown. In FIG. 3A, the openings of the solder resist layer at the uppermost layer are indicated by dashed circles. In FIGS. 3B to 3D, positions of the via conductors connected to the conductor layer at the upper layer are indicated by dashed circles, and the sign G, the sign P and the sign S in these circles represent the via conductors for grounding, for power supply, and for signal, respectively.
As shown in FIG. 3A, the conductor layer 11 at the uppermost layer includes patterns 11a to 11d shown in the following (a) to (d):
(a) the signal pattern 11a forming a semiconductor element connection pad for signal S individually;
(b) the grounding plane 11b connecting the semiconductor element connection pads for grounding G on the column L1 and the column L2 to one, and extending to the outside of the mounting portion A;
(c) the grounding pattern 11c connecting the semiconductor element connection pads for grounding G on the column L5 and the column L4 to one; and
(d) the power supply pattern 11d connecting the semiconductor element connection pads for power supply P on the column L3 and the column L4 to one.
As shown in FIG. 3B, the conductor layer 12 formed below the conductor layer 11 includes patterns 12a to 12d shown in the following (a) to (d):
(a) the strip-shaped signal wiring pattern 12a extending from the bottom of the semiconductor element connection pad for signal S to the outside of the mounting portion A;
(b) the grounding plane 12b adjacent to the signal wiring pattern 12a, extending to the outside of the mounting portion A;
(c) the grounding pattern 12c formed in the same position as the grounding pattern 11c at the upper layer; and
(d) the land pattern for power supply 12d arranged so as to be separated by the signal wiring pattern 12a below a part of the semiconductor element connection pads for power supply P.
Each of the signal wiring patterns 12a is connected to the corresponding one of the signal patterns 11a at the upper layer through one via conductor. The grounding plane 12b and the grounding pattern 12c are respectively connected to the grounding plane 11b and the grounding pattern 11c at the upper layer through a plurality of via conductors. The land pattern for power supply 12d is connected to the power supply pattern 11d at the upper layer through a plurality of via conductors.
As shown in FIG. 3C, the conductor layer 13 formed below the conductor layer 12 includes a solidly spread grounding plane 13a and a land pattern for power supply 13b. The grounding plane 13a is connected to the grounding plane 12b and the grounding pattern 12c at the upper layer through a plurality of via conductors. The land pattern for power supply 13b is connected to the land pattern 12d at the upper layer through a plurality of via conductors.
As shown in FIG. 3D, the conductor layer 14 formed below the conductor layer 13 includes a power supply plane 14a and a land pattern for grounding 14b. The power supply plane 14a is connected to the land pattern 13b at the upper layer through a plurality of via conductors. Thereby, the semiconductor element connection pads for power supply P and the power supply plane 14a are electrically connected to each other through the land patterns for power supply 12d and 13b. 
However, in such a conventional wiring board, the land pattern for power supply 12d of the conductor layer 12 connected to the power supply pattern 11d forming the semiconductor element connection pads for power supply P in the segment region B through the via conductors is divided by the signal wiring pattern 12a, and the area becomes smaller. Therefore, the inductance of the current path between the semiconductor element connection pads for power supply P and the power supply plane 14a connected to each other through the via conductors with the land patterns for power supply 12d and 13b interposed therebetween is increased. As a result, there has been a problem that the sufficient power is not supplied in each segment region B, and that it is difficult to sufficiently exert the capability of the semiconductor element to be mounted.